SED1234/35 series 1 pf833-01 dot matrix lcd controller driver SED1234/35 series n overview the SED1234, 1235 series is a dot matrix lcd controller driver for character display, and can display a maximum of 48 characters, 4 user-defined characters, and a maximum of 48 symbols by means of 4-bit, 8-bit or serial data sent from a microcomputer. a built-in character generator rom is prepared for 256 character types, and each character font consists of 5 x 7 dots. a user-defined character ram for four characters of 5 x 7 dots are incorporated, and a symbol register is also incorporated. with these, it is possible to apply this series to display with a high degree of freedom. this series can operate handy units with a minimum power consumption by means of its low power consumption and sleep mode. SED1234, and 1235 depending on the duty of use and the number of display columns. n features l built-in display ram 48 characters + 4 user-defined characters + 48 symbols l cg rom (for up to 256 characters), cg ram (4 characters), and symbol register (48 symbols) l number of display columns x number of lines (12 columns + 2 segment for signal) x 4 lines + 48 symbols: SED1234 (12 columns + 2 segment for signal) x 2 lines + 48 symbols: sed1235 l cr oscillation circuit (on-chip c and r) l high-speed mpu interface interfacing with both 68 series and 80 series mpu interfacing in 4 bits/8 bits l serial interface l character font 5 x 7 dots l duty ratio 1/16 (sed1235) 1/30 (SED1234) l simple command setting l built-in liquid crystal driving power circuit power boosting circuit, power regulating circuit, voltage follower x 4 l built-in electronic volume function l low power consumption 100 m a max. (in normal operation mode: including the operating current of the built-in power supply) l power supply v dd - v ss (logic section): C2.4 v to C3.6 v v dd - v 5 (liquid crystal drive section): C5.0 v to C8.0 v l wide operating temperature range ta = C30 to 85 c l cmos process (pad pitch) l cob assemble 126 m m min. l delivery form: chip sed123 ] d * a , sed123 ] d * c l this ic is not designed with a protection against radioactive rays. l 12 chara x 4 line (5 x 7 dot) l built-in character generator rom and ram l built-in power supply circuit for lcd
2 SED1234/35 series n block diagram power circuit oscillator v s1 v out v 5 com1~28 coms2,3 seg1~60 segs2,6 seg driving circuit command decoder com driving circuit cursor control v 1 v 2 v 3 v 4 v r cap2 cap2+ cap1 cap1+ if res a0 cs wr (e) p/s d0 d7 (si) d6(scl) d5 d4 d3 d2 d1 timing generating circuit refresh address counter ram cg rom address counter input buffer mpu interface
SED1234/35 series 3 ? chip specification SED1234d ** 1/30 duty sed1235d ** 1/16 duty #1 column for cg rom pattern change chip size: 10.23 x 3.11 mm pad pitch: 126 m m (min.) chip thickness: 625 25 m m (sed123 ] d * a ) 525 25 m m (sed123 ] d * c ) 1) al pad specification pad size: a 91 m m x 90 m m b 114 m m x 114 m m - 109 33 110 127 17 16 14 15 3 12 21 32 22 : nc (make it floating.)
4 SED1234/35 series ? absolute maximum ratings notes: 1. all the voltage values are based on v dd = 0 v. 2. for voltages of v 1 , v 2 , v 3 and v 4 , keep the condition of v dd > = v 1 > = v 2 > = v 3 > = v 4 > = v 5 and v dd > = v ss > = v 5 > = v out at all times. 3. if the lsi is used exceeding the absolute maximum ratings, it may lead to permanent destruction. in ordinary operation, it is desirable to use the lsi in the condition of electrical characteristics. if the lsi is used out of this condition, it may cause a malfunction of the lsi and have a bad effect on the reliability of the lsi. item symbol standard value unit power supply voltage (1) v ss C6.0 to +0.3 v power supply voltage (2) v 5 C16.0 to +0.3 v power supply voltage (3) v 1 , v 2 , v 3 , v 4 v 5 to +0.3 v input voltage v in v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v operating temperature t opr C30 to +85 c storage temperature tcp t str C55 to +100 c bare chip C65 to +125 (v cc ) v dd (gnd) v ss v dd v 5
SED1234/35 series 5 input voltage v ss C3.6 C2.4 v *10 booster output voltage v out double boosting state C7.2 v v out triple boosting state C10.8 voltage follower v 5 C11.0 C4.5 v operating voltage reference voltage v reg ta = 25 c C3.5 C3.1 C2.7 v *12 (standard) reference voltage v reg(vs1) ta = 25 c C2.4 C2.1 C1.8 v *12 (option) item symbol condition min typ max unit applicable pin power recommended C3.6 C3.0 C2.4 v v ss supply operation v ss voltage (1) operable C5.5 C3.0 C2.4 *1 power recommended C8.0 C5.0 v v 5 supply operation v 5 voltage (2) operable C11.0 C4.5 *2 operable v 1 , v 2 0.6 v 5 v dd vv 1 , v 2 operable v 3 , v 4 v dd 0.4 v 5 vv 3 , v 4 high-level input voltage v ihc 0.2 v ss v dd v*3 low-level input voltage v ilc v ss 0.8 v ss v*3 input leakage current i li v in = v dd or v ss C1.0 1.0 m a*3 lc driver on resistance r on ta=25 cv 5 =C7.0v 20 40 k w com,seg d v=0.1v *4 static current consumption i ddq 0.1 5.0 m av dd dynamic current i dd display state v 5 = C7 v without load 100 m av dd *5 consumption standby state oscillation on, 20 m av dd *6 power off sleep state oscillation off, 5 m av dd power off access state f cyc =200khz 500 m av dd *7 frame frequency f fr ta=25 c v ss =C3.0v 70 100 130 hz *11 input pin capacity c in ta=25 c f=1mhz 5.0 8.0 pf *3 ? dc characteristics (v dd = 0 v, v ss = C3.6 v to C2.4 v, ta = C30 to 85 c unless otherwise specified.) built-in power supply *1: a wide operating voltage range is guaranteed but an abrupt voltage variation in the access status of the mpu is not guaranteed. *2: the operating voltage range is applicable to the case where an external power supply is used. *3: d0 to d5, d6 (scl), d7 (si), a0, res, cs wr (e), p/ s, if *4: this is a resistance value when a voltage of 0.1 v is applied between output pin segn, segsn, comn or comsn, and each power pin (v1, v2, v3 or v4). it is specified in the range of operating voltage (2). r on = 0.1 v / d i ( d i: current flowing when 0.1 v is applied between the power and output) *5: character " " display. this is applicable to the case where no access is made from the mpu and the built-in power circuit and oscillating circuit are in operation. reset time t r 1.0 m s*8 reset pulse width t rw 10 m s*9 reset start time t res 50 ns *9
6 SED1234/35 series sed123 * d a * lower 4 bit of code 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f higher 4 bit of cord
SED1234/35 series 7 sed123 * d b * lower 4 bit of code 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f higher 4 bit of cord
8 SED1234/35 series sed123 * d g * lower 4 bit of code 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f higher 4 bit of cord
10 SED1234/35 series notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aris ing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no re presentation that this material is applicable to products requiring high level reliability, such as, medical products. morever, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material wil l be free from any patent or copyright infringement of a third party. this material or portions thereof may contain techonology or the subject re lating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license fro m the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1996 all right reserved. electronic device marketing department ic marketing & engineering group 421-8 hino, hino-shi, tokyo 191, japan phone: 0425-87-5816 fax: 0425-87-5624 international marketing department i (europe, u.s.a.) 421-8 hino, hino-shi, tokyo 191, japan phone: 0425-87-5812 fax: 0425-87-5564 international marketing department ii (asia) 421-8 hino, hino-shi, tokyo 191, japan phone: 0425-87-5814 fax: 0425-87-5110 issue nov. 1996, printed in japan h
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